The present invention relates to line interface devices and, in particular, to a high speed Futurebus+ data transceiver that meets the IEEE 1194.1 standard for backplane transceiver logic (BTL).
A data transceiver (TRANSmitter/reCEIVER) is a read/write terminal capable of transmitting information to and receiving information from a transmission medium. A transceiver typically includes a line driver stage and a receiver stage. The line driver amplifies digital signal outputs from a computer system so that the signals can be properly transmitted on the transmission medium. Conventional line drivers usually include level shifting capability to provide compatibility with different integrated circuit technologies (e.g., TTL) that might be used in the computer's internal logic. The receiver is typically a differential amplifier that receives signals from the transmission medium and provides an output representative of digital information received from the medium.
Transceiver circuits may be designed for general-purpose applications or may be designed for a more specific, industry standard data-communications configuration.
One such industry standard is the so-called IEEE 896.1 Futurebus+ standard. The Futurebus+ standard provides a protocol for implementing an internal computer bus architecture.
FIG. 1 shows the hierarchy of bus levels utilizable in a Futurebus+ system.
FIG. 2 shows the positioning of a data transceiver between the backplane bus of a Futurebus+ system and the data bus of a processor internal to that system to facilitate communications between the processor and the rest of the system.
While integrated circuit versions of data transceivers utilizable in conjunction with Futurebus+ architectures have been available, both the driver stages and receivers of these transceivers have exhibited deficiencies. With respect to the driver stages, past Futurebus+ transceivers exhibit unsymmetrical skew; that is, the high to low transitions are too fast and the low to high transitions are too slow. Furthermore, conventional Futurebus+ drivers exhibit poor temperature and supply performance and consume too much power. On the receiver side, conventional Futurebus+ transceiver implementations exhibit enormous ground bouncing, with attendant stability and skew problems.
Therefore, it would be highly desirable to have available a data transceiver that is utilizable in Futurebus+ applications and that provides slew rate control, exhibits better temperature and supply AC performance and consumes less power.